Computer Architecture : Instruction set Architecture

The instruction set is the set of basic instructions that a processor understands. The instruction set is a portion of what makes up an architecture. It is a group of commands for a CPU in machine language. The term can refer to all possible instructions for a CPU or a subset of instructions to enhance its performance in certain situations. The instruction set provides commands to the processor, to tell it what it needs to do. The instruction set consists of addressing modes, instructions, native data types, registers, memory architecture, interrupt, and exception handling, and external I/O. n example of an instruction set is the x86 instruction set, which is common to find on computers today. Different computer processors can use almost the same instruction set while still having very different internal design. Both the Intel Pentium and AMD Athlon processors use nearly the same x86 instruction set. An instruction set can be built into the hardware of the processor, or it can be emulated in software, using an interpreter. The hardware design is more efficient and faster for running programs than the emulated software version. Some examples of instruction set are given below :

  • ADD :               Add two numbers together
  • COMPARE :     Compare numbers
  • IN :                   Input information form a device, e.g., keyboard
  • JUMP :             Jump to designated RAM address.
  • JUMP IF :         Conditional statement that jumps to a designated RAM address.
  • LOAD :             Load information from RAM to the CPU.
  • OUT :                Output information to device, e.g., monitor.
  • STORE :            Store information to RAM.

The Instruction Set Architecture (ISA) is the part of the processor that is visible to the programmer or compiler writer. The ISA serves as the boundary between software and hardware. The Instruction Set Architecture can be described using 5 categories :

  • Operand Storage in the CPU : Where are the operand kept other than in memory.
  • Number of Explicit Operand : How many operands are in a typical instruction.
  • Operand location : Can any ALU (Arithmetic Logic Unit) instruction operand be located in memory ? or must all operands be kept internally in the CPU ?
  • Operations : What operations are provided in the Instruction Set Architecture.
  • Type and size of Operands : What is the type and size of each operand and how is it specified?

All the above points are the distinguishing factors which described the Instruction Set Architecture of a processor. There are three common types of Instruction Set Architecture, which are : 

1. Stack : A stack is a linear array of address.  It is also known as a push down list or last-in-first-out queue. The stack is previously saved block of addresses. Items are always added to the top of the stack so that, at any given time, the block is filled in parts. The stack posses a pointer whose value is the address of the top of the stack. The operands are implicitly on top of the stack. For example, lets see that the assembly code of A = B + C is what looks like in stack :


2. Accumulator : The accumulator is located inside the ALU, It is used during arithmetic & logical operations of ALU. The control unit stores data values fetched from main memory in the accumulator for arithmetic or logical operation. During the processing one operand is implicitly in the accumulator. For example, lets see that the assembly code of A = B + C is what looks like in accumulator :


3. General Purpose Register (GPR) : The general purpose register can store a data or a memory location address. Hence called as General purpose register. It is a multipurpose register. It is available to store any transient data required by the program. For example, when a program is interrupted its state, ie: the value of the registers such as the program counter, instruction register or memory address register - may be saved into the general purpose registers, ready for recall when the program is ready to start again. In general the more registers a CPU has available, the faster it can work. During the processing all operands are explicitly mentioned, they are either registers or memory locations. For example, lets see that the assembly code of A = B + C is what looks like in GPR :


Earlier CPUs were consists only first two types Stack and Accumulator. But in the last 20 years all CPUs made are GPR processors. The two major reasons are that registers are faster than memory, the more data that can be kept internally in the CPU the faster the program will run. The other reason is that registers are easier for a compiler to use.

We can also classified Instruction Set Architecture by Architectural complexity. Which are as follows :

  • CISC
  • RISC

CISC ( Complex Instruction Set Computing ) : The term CISC or Complex Instruction Set Computing refers to computers designed with a full set of computer instructions that were intended to provide needed capabilities in the most efficient way. The CISC approach attempts to minimize the number of instructions per program, sacrificing the number of cycles per instruction. Computers based on the CISC architecture are designed to decrease the memory cost. Because, the large programs need more storage, thus increasing the memory cost and large memory becomes more expensive. To solve these problems, the number of instructions per program can be reduced by embedding the number of operations in a single instruction, thereby making the instructions more complex.

RISC ( Reduced Instruction Set Computing ) : RISC or Reduced Instruction Set Computing refers to  microprocessors that designed to perform a smaller number of types of computer instructions so that it can operate at a higher speed (perform more millions of instructions per second, or MIPS). Since each instruction type that a computer must perform requires additional transistors and circuitry, a larger list or set of computer instructions tends to make the microprocessor more complicated and slower in operation. RISC is a type of microprocessor architecture that uses highly-optimized set of instructions. RISC does the opposite, reducing the cycles per instruction at the cost of the number of instructions per program Pipelining is one of the unique feature of RISC. It is performed by overlapping the execution of several instructions in a pipeline fashion. It has a high performance advantage over CISC.

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