Computer Architecture : Machine Instruction Cycle

In Computing, An Instruction cycle, also known as fetch-decode-execute cycle is the basic operational process of a computer. The processing needed for a single instruction (fetch and execution) is referred to as instruction cycle. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instructions dictates, and carries out those actions. The instruction cycle consist of the fetch cycle and the execute cycle. This cycle is repeated continuously by a computer's Central Processing Unit, from boot-up to when the computer is shut down. The major responsibility in Instruction cycle is with the CPU. The instruction execution takes place in the CPU registers. Let us, first discuss few typical registers and other components, some of which are commonly available in of the machines.

Memory Address Register (MAR) : The Memory Registers specifies the address of memory location from which data or instruction is to be accessed (for read operation) or to which the data is to be stored (for write operation).

Program Counter (PC) : The Program Counter keeps track of the memory address of the instruction that is to be executed next or in other words, holds the address of the instruction to be executed next.

Instruction Register (IR) : The Instruction register is a part of CPU control unit that stores the instruction currently being executed or decoded or in other words it contains the instructions are loaded before their execution.

Memory Buffer Register (MBR) : The Memory Buffer Register is a two-way register that holds data fetched from memory (and ready for the CPU to process) or data waiting to be stored in memory. It is also known as MDR or Memory Data Register.

Control Unit (CU) : The Control Unit Decodes the program instruction in the IR, selecting machine resources, such as a data source register and a particular arithmetic operation, and coordinates activation of those resources.

Arithmetic Logic Unit (ALU) : The ALU performs the mathematical and logical operations.

Floating Point Unit (FPU) : FPU performs mathematical and logical operations.

Accumulator (AC) :  An accumulator register is a intermediate storage of arithmetic and logic data in a computer's CPU (central processing unit).

In CPUs the instruction cycle is executed sequentially, each instruction being processed before the next one is started. An instruction cycle consist of the following sub-cycles :

1. Fetch The Instruction : It reads the next instruction from memory into the CPU. The next instruction is fetched from the memory address that is currently stored in the program counter and stored into the instruction register. At the end of the fetch operation,  PC is incremented by 1 and it points to the next instruction that will be read at the next cycle.

2. Decode The instruction : During this cycle the encoded instruction present in the instruction register is interpreted by the decoder.

3. Read The Effective Address : If the instruction has an indirect address, the effective address is read from the memory. Otherwise operands are directly read in case of immediate operand instruction.

4. Execute The instruction : The control unit of the CPU passes the decoded information as a sequence of control signals to the relevant function units of the CPU to perform the actions required by the instruction such as reading values from registers, passing them to the ALU to perform mathematical or logic functions on them, and writing the result back to a register. If the ALU is involved, it sends a condition signal back to the CU. The result generated by the operation is stored in the main memory or sent to an output device. Based on the feedback from the ALU, the PC may be updated to a different address from which the next instruction will be fetched.

5. Interrupt : During the process execution if interrupt occured, then it saves the current process status and service the interrupt.

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