Processor Implementation : Single Cycle & Multi Cycle

Single-Cycle Processor :

A single cycle processor is a processor that carries out one instruction in a single Clock cycle. With the single cycle implementation the processor will consist of two cooperating units : Datapath and Control unit. In single cycle processor the Control unit is responsible for setting all the control signals so that each instruction is executed properly and the Datapath contains all the functional units and connections necessary to implement an instruction set architecture. The Control unit tells the datapath what to do, based on the instruction that's currently being executed. The single cycle processor will perform each instruction in 1 clock cycle. The clock cycle must be long enough for slowest instruction.


Figure : Single Cycle Processor

Single-cycle processors suffer from poor speed performance. Control and data signals must propagate completely through the processor in a single cycle, which means that cycle times need to be long, and many parts of the hardware tend to be dormant for much of the cycle.

Disadvantage of a Single Cycle Processor :

1. The Cycle time is much longer than needed for all other instructions.
2. All instructions take same time as the slowest instruction.
3. only as fast as slowest instruction.


Multi-Cycle Processor :

Multi-cycle processors break up the instruction into its fundamental parts, and executes each part of the instruction in a different clock cycle. Since signals have less distance to travel in a single cycle, the cycle times can be sped up considerably. In multicycle approach the instruction execution is performed as a sequence of small steps or actions. Instead of trying to perform all these actions in one giant cycle, it partition them into groups that are performed in order one after the other. In multi-cycle approach, typically an instruction is executed over at least five cycles, which are :

1. Read instruction from memory.
2. Decode instruction and speculatively read two registers that the instruction might use
3. Perform ALU calculations or access memory.
4. Write result back to register file.
5. Determine next PC and update PC.


Figure : Multi-Cycle Processor

Because these steps will be executed in separate cycles, it is necessary to introduce additional storage elements to remember what step of the execution we are at and to hold information as long as it might needed. The above figure shows the Multi-Cycle processor. We will notice that it is slightly different than the single cycle datapath. One key difference is the introduction of temporary registers to hold the outcomes that are produced at each cycle. The following temporary registers are introduced: 

IR or Instruction Register : This is used to hold the instruction encoding after it is read from memory. A register is needed because we will use a single memory device both for data and instructions. Accordingly, its output may change during the execution of an instruction (a load will read from memory).

R1 and R2 : These are used to temporarily hold the register values read from the register file.

AluOut : This is used to temporarily hold the result calculated by the ALU.

MDR or Memory Data Register : Holds the value returned from memory so that it can later be written into the register file.


Disadvantage of a Multi-Cycle Processor :

In Multi-cycle processor each instruction uses only as many cycles as it needs.




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