Advanced DRAM Organization

Dynamic random access memory is a type of random access memory that stores each bit of data in a separate capacitor within an integrated circuit. Since the capacitor is always leaking, the stored information eventually disappears unless the capacitor is refreshed periodically. Because of the need in refreshment, this makes it very dynamic compared to memory (SRAM) static memory and others. The advantage of DRAM is its structural simplicity: only one transistor and capacitor is required per bit, compared to four in the SRAM Transistor. This allows DRAM to reach very high densities. Unlike flash memory, DRAM memory is easily "evaporated" due to loss of data when loss of power.

The traditional DRAM is constrained both by its internal architecture and by its interface to processor's memory bus. One of the most critical system bottlenecks when using high-performance processors is the interface to main memory. This interface is the most important pathway in the entire computer system. The basic building block of main memory remains the DRAM chip. So in recent years to improve the performance of DRAM, a number of enhancements to the basic DRAM architecture have been explored, and some of these are :

1. Synchronous DRAM (SDRAM)
2. Rambus DRAM (RDRAM)
3. Double Data Rate DRAM (DDR DRAM)
4. Cache DRAM (CDRAM)

1. Synchronous DRAM (SDRAM) : SDRAM or for short Synchronous DRAM, is a type of memory that synchronizes itself with the computer's system clock. Being synchronized allows the memory to run at higher speeds than previous memory types and asynchronous DRAM and also supports up to 133 MHz system bus cycling. SDRAM exchanges data with the processor synchronized to an external clock signal and running at the full speed of the processor/memory bus without imposing wait states. SDRAM employs a burst mode to eliminate the address setup time and row and column line precharge time after the first access. In burst mode a series of data bits can be clocked out rapidly after the first bit has been accessed. It has a multiple bank internal architecture that improves opportunities for on chip parallelism. SDRAM performs best when it is transferring large blocks of data serially.

2. Rambus DRAM (RDRAM) : Rambus Dynamic Random Access Memory (RDRAM) is a memory subsystem designed to transfer data at faster rates. RDAM is made up of a random access memory (RAM), a RAM controller and a bus path that connect RAM to microprocessors and other PC devices. Typical SDRAM has a data transfer rate of up to 133 MHz, while the RDRAM can transfer data at a speed of upto 800 MHz. RDRAM is also known as Direct RDRAM or Rambus. RDRAM uses Rambus Inline Memory Module (RIMM) technology, which is installed in pairs, transfers data from rising and falling clock signal edges and doubles physical clock rates. Concurrent RDRAMs have been used in video games, while Direct RDRAMs have been used in computers.

3. Double Data Rate DRAM (DDR DRAM) : Double data rate (DDR) is the advanced version of synchronous dynamic random access memory (SDRAM). SDRAM waits for clock signals before responding to control inputs. It uses both rising (positive edge) and falling (negative) edge of clock for data transfer. That is DDR SDRAM can send data twice per clock cycle - once on the rising edge of the clock pulse and once on the falling edge. The difference between SDRAM and DDR is not the speed, but rather how many times data is transmitted with each cycle. DDR transfers data twice per clock cycle, whereas SDRAM sends signals once per clock cycle. The same frequencies are used for both. However, DDR uses both edges of the clock, whereas SDRAM uses only one. DDR is outdated but is still in use, such as for the output of analog-to-digital converters. Updated DDR versions are DDR2 and DDR3. The later generations (DDR2 and DDR3) increases the data rate by increasing the operational frequency of the RAM chip and by increasing the prefetch buffer from 2 bits to 4 bits per chip.

4. Cache DRAM (CDRAM) : A DRAM with an on-chip cache is called the cache DRAM. It is a hierarchical RAM containing a 1-Mb DRAM for the main memory and an 8-kb SRAM (static RAM) for cache memory. It uses a 1.2- mu m CMOS technology. This architecture achieves concurrent operation of DRAM and SRAM synchronized with an external clock. Separate control and address input terminals of the two portions enable independent control of the DRAM and SRAM, thus the system achieves continuous and concurrent operation of DRAM and SRAM. CDRAM can handle CPU, direct memory access (DMA) and video refresh at the same time by utilizing a high-speed video interface. CDRAM is suitable for no-wait-state memory access in low-end workstations and personal computers, the chip also serves high-end systems as a secondary cache scheme.

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