Computer Architecture : RISC Pipeline

In RISC(Reduced Instruction Set Computer) processors, Pipelining is a standard feature. A pipeline is the continuous and somewhat overlapped movement of instruction to the processor or in the arithmetic steps taken by the processor to perform an instruction. It allows storing and executing instructions in an orderly process. We can compare Pipelining with a manufacturing assembly line in which different parts of a product are being assembled at the same time although ultimately there may be some parts that have to be assembled before others are. Even if there is some sequential dependency, the overall process can take advantage of those operations that can proceed concurrently. A RISC processor pipeline operates in much the same way, although the stages in the pipeline are different. While different processors have different numbers of steps, they are basically variations of these five stages or segments :

  • FI = Fetch instruction from memory
  • DI = Decode the Instruction
  • FO = Fetch Operand from data memory
  • EX = Execute Instruction
  • WO = Write back Operand

The execution of the instruction comprising of the above given segments or sub-task can be pipelined. Each of the clock cycles from the previous section becomes a pipe stage – a cycle in the pipeline. A new instruction can be started on each clock cycle which results in the execution pattern shown in below figure. Though each instruction takes 5 clock cycles to complete, during each clock cycle the hardware will initiate a new instruction and will be executing some part of the five different instructions as illustrated in below figure.

Each stage of the pipeline must be independent of the other stages. Also, two different operations can’t be performed with the same data path resource on the same clock. For example, a single ALU cannot be used to compute the effective address and perform a subtract operation during the same clock cycle.

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