Computer Architecture : RISC Processors

An important aspect of computer architecture is the design of the instruction set for the processor. In the early 1980s, a number of computer designer recommended that computers use fewer instructions with simple constructs so they can be executed much faster within the CPU without having to use memory as often. This type of computer is classified as a Reduced Instruction Set Computer or RISC.

The idea of RISC architecture is try to minimize the execution time by simplifying the instruction set of the computer. The small set of instructions of a RISC processor made up of register-to-register operations with only simple load and store operations for memory access. So each operand is transferred into a processor register with a load instruction. All calculation are performed among the data stored in processor registers. Results are moved to memory with the help of store instruction. This architectural feature simplifies the instruction set and promote the optimization of register manipulation. The use of only a few addressing technique occurs from the fact that almost all instructions have simple register addressing. Other addressing technique may be taken into account, such as immediate operands and relative mode.


RISC is a type of microprocessor architecture that uses highly-optimized set of instructions. RISC processors reduce the cycles per instruction at the cost of the number of instructions per program Pipelining is one of the unique feature of RISC. It is performed by overlapping the execution of several instructions in a pipeline fashion. It has a high performance advantage over CISC.

The major characteristics of a RISC processor are :

  1. Relatively less instructions are used in RISC processors.
  2. RISC utilizes simple addressing modes and fixed length instructions for pipelining.
  3. Single-Cycle instruction execution.
  4. The amount of work that a computer can perform is reduced by separating “LOAD” and “STORE” instructions.
  5. RISC contains Large Number of Registers in order to prevent various number of interactions with memory.
  6. In RISC Architecture, All operations performed within the registers of the CPU.
  7. The simplicity of RISC allows more freedom to choose how to use the space on a microprocessor.
  8. In RISC Architecture, more RAM is required to store assembly level instructions.






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