Instruction Pipeline

In Instruction Pipeline the instructions can be executed by overlapping fetch, decode and execute phases of an instruction cycle. This type of technique is used to increase the throughput of the computer system. An instruction pipeline reads instructions from one after another memory while previous instructions are being executed in other segments of the pipeline. This results in the instruction fetch and execute phases to overlap and does the simultaneous operations. Thus we can execute multiple instructions simultaneously. The below figure represent how the instruction cycle can be processed by CPU with a four-segment pipeline.

At the above figure while an instruction is being executed in segment 4, the next instruction in sequence is engaged in fetching an operand from memory in segment 3. The effective address may be calculated in a different arithmetic circuit for the third instruction and if the memory is avaliable the fourth and all the next instructions can be fetched and kept in an instruction FIFO. So up to four sub-operations in the instruction cycle can overlap and four different instruction can be in progress of being processed at the same time. An instruction in the sequence may be a program control type that result in a branch out of normal sequence, In such situation the pending operations in the last two segments are finished and all information stored in the instruction buffer is deleted. The pipeline then begins from the new address stored in the program counter. Similarly an interrupt request when found will result in the pipeline to empty and start again from a new address value. The instruction Pipeline has four segments :

  • Fetch Instruction (FI)
  • Decode Instruction (DI)
  • Fetch Operands (FO)
  • Execute Instructions (EX)

Fetch Instruction (FI) : The FI segment is responsible for obtaining the requested instruction from memory.

Decode Instruction (DI) : The DI segment is responsible for decoding the instruction.

Fetch Operands (FO) : The FO segment is responsible for fetching the operands from memory.

Execute Instructions (EX) : The EX segment is responsible for Executing the instruction.

The below figure represents the operation of the instruction pipeline. 

The time in the horizontal axis is partitioned into steps of same duration. Now let us considered that the processor has different instruction and data memories so that the operation in FI or FO can move forward at the same time. In the absence of a branch instruction, each segment work on different instructions. So in Step 4, instruction 1 is executed in segment EX. The operand for instruction 2 is fetched in segment FO, instruction 3 is decoded in segment DI, and instruction 4 is fetched from memory in segment FI. Now consider that instruction 3 is a branch instruction. When instruction is decoded in segment DI in step 4 the movement from FI to DI of the other instructions is halted until the branch instruction is executed in step 6. If the branch is executed, a new instruction is is fetched in step 7, otherwise the instruction fetched previously in step 4 can be used. The pipeline then repeats until a new branch instruction is occurred. 

More delay may occur in the pipeline if the EX segment require to store the result of the operation in the data memory while the FO segment requires to fetch an operand. In such situation segment FO must wait until segment EX has completed its operation.

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