Pipeline Hazard

The conditions in pipelining that causes the pipeline to stall is called a hazard. The situations, that prevent the next instruction in the instruction stream from being executing during its designated clock cycle, is known as Hazards. Hazards reduce the performance from the ideal speedup gained by pipelining. There are three types of Hazards in Pipelining :


  • Structural hazards
  • Data hazards
  • Control hazards


1. Structural Hazards : 

Structural hazard arises from resource conflicts, when a machine is pipelined, the overlapped execution of instructions requires pipelining of functional units and duplication of resources to allow all posible combinations of instructions in the pipeline. If some combination of instructions cannot be accommodated because of a resource conflict, the processor is said to have a structural hazard. For example, suppose the processor only has a single port to memory used for both data and instructions. Then there is a structural hazard between the FI and FO segment. 


To solve this hazard, we 'stall' the pipeline until the resource is freed. A stall is commonly called pipeline bubble, since it floats through the pipeline taking space but carry no useful work.


2. Data hazards :

A Data hazard is any condition in which either the source or the destination operands of an instruction are not available at the time expected in the pipeline. As a result some operation has to be delayed, and the pipeline stalls. For example consider the pipelined execution of the following instruction sequence


All the instructions after the ADD use the result of the ADD instruction (in R1). The ADD instruction will execute at 4th clock cycle (denoted in orange box), and the SUB instruction reads the value during DI stage (denoted in red color at clock cycle 3). This problem is called a data hazard. Unless precautions are taken to prevent it, the SUB instruction will read the wrong value and try to use it. Similarly the AND instruction is also affected by this data hazard. The ADD instruction does not complete until the end of 4th cycle clock. Thus, the AND instruction that reads the registers during clock cycle 4 will receive the wrong result. But the OR instruction operates properly, because its register read occur in clock cycle 5 after the ADD instruction is completed. similarly the XOR instruction also operates properly, because its register read occur in clock cycle 6.


3. Control Hazards :

Control hazards can cause a greater performance loss for pipelining than data hazards. When a branch is executed, it may or may not change the PC (program counter) to something other than its current value plus 4. If a branch changes the PC to its target address, it is a taken branch; if it falls through, it is not taken.


The simplest scheme to handle branches is to freeze the pipeline holding or deleting any instructions after the branch until the branch destination is known. The attractiveness of this solution lies primarily in its simplicity both for hardware and software.




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