Computer Architecture : I/O Bus

A personal computer may transfer data from disk to CPU, from CPU to memory, or from memory to the display adapter. A PC cannot afford to have separate circuits between every pair of devices. A mechanical switch, like the old phone systems used, would be too slow. The solution is a Bus.

The Bus is simply a common set of wires that connect all the computer devices and chips together. Some of these wires are used to transmit data. Some send housekeeping signals, like the clock pulse. Some transmit a number (the "address") that identifies a particular device or memory location. The computer chips watch the address wires and respond when their identifying number is transmitted. They then transfer data on the other wires.

In a modern PC, there may be a half dozen different Bus areas. There is certainly a "CPU area" that still contains the CPU, memory, and basic control logic. There is a "High Speed I/O Device" area that is either a VESA Local Bus (VLB) or an PCI Bus. An very low cost home computer may have no high speed devices. A more typical desktop system connects the high speed bus on the main-board to the display adapter and IDE disk interface chip. Then one or two extra I/O slots may allow adapter cards to connect to the high speed bus. The remaining I/O device slots support standard "ISA" bus cards. Some computers will also provide sockets for a number of PCMCIA "credit card" adapters commonly found in laptop computers.

The processor, main memory, and I/O devices can be interconnected through common data communication lines which are termed as common bus. The primary function of a common bus is to provide a communication path between the devices for the transfer of data. The bus includes the control lines needed to support interrupts and arbitration. The bus lines used for transferring data may be grouped into three categories:

  • Data 
  • Address
  • Control lines

A single  Read/Write line is used to indicate Read or Write operation. When several sizes are possible like byte, word, or long word, control signals are required to indicate the size of data. The bus control signal also carry timing information to specify the times at which the processor and the I/O devices may place data on the bus or receive data from the bus. There are several schemes exist for handling the timing of data transfer over a bus. These can be broadly classified as :

  • Synchronous bus
  • Asynchronous bus

Synchronous Bus : 

In a synchronous bus, all the devices are synchronized by a common clock, so all devices derive timing information from a common clock line of the bus. A clock pulse on this common clock line defines equal time intervals. In the simplest form of a synchronous bus, each of these clock pulse constitutes a bus cycle during which one data transfer can take place. The timing of an input transfer on a synchronous bus is shown in the Figure below :

Let us consider the sequence of events during an input (read) operation. 
  • At time t0, the master places the device address on the address lines and sends an appropriate command (read in case of input) on the command lines. 
  • In any data transfer operation, one device plays the role of a master, which initiates data transfer by issuing read or write commands on the bus. 
  • Normally, the processor acts as the master, but other device with DMA capability may also becomes bus master. The device addressed by the master is referred to as a slave or target device. 
  • The command also indicates the length of the operand to be read, if necessary. 
  • The clock pulse width, t1 - t0, must be longer than the maximum propagation delay between two devices connected to the bus. 
  • After decoding the information on address and control lines by slave, the slave device of that particular address responds at time t1. The addressed slave device places the required input data on the data line at time .

At the end of the clock cycle, at time t2, the master strobes the data on the data lines into its input buffer. The period t2- t1 must be greater than the maximum propagation delay on the bus plus the set up time of the input buffer register of the master. A similar procedure is followed for an output operation. The master places the output data on the data lines when it transmits the address and command information. At time t2, the addressed device strobe the data lines and load the data into its data buffer.

Asynchronous Bus :

In asynchronous mode of transfer, a handshake signal is used between master and slave. In asynchronous bus, there is no common clock, and the common clock signal is replaced by two timing control signals: master-ready and slave-ready. Master-ready signal is assured by the master to indicate that it is ready for a transaction, and slave-ready signal is a response from the slave. The handshaking protocol proceeds as follows:

  • The master places the address and command information on the bus. Then it indicates to all devices that it has done so by activating the master-ready signal.
  • This causes all devices on the bus to decode the address.   
  • The selected target device performs the required operation and inform the processor (or master) by activating the slave-ready line.   
  • The master waits for slave-ready to become asserted before it remove its signals from the bus.  
  • In case of a read operation, it also strobes the data into its input buffer.

The timing of an input data transfer using the handshake scheme is shown in the Figure below :

The timing of an output operation using handshaking scheme is shown in the Figure below :

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