PowerPC Cache Organization

The PowerPC cache organization has evolved with the overall architecture of the PowerPC family, reflecting the relentless pursuit of performance that is the driving force for all microprocessor designers.

PowerPC Internal Caches :
  • 601 – single 32kB 8 way set associative 
  • 603 – 16kB (2 x 8kB) two way set associative 
  • 604 – 32kB 
  • 610 – 64kB 
  • G3 & G4 -  64kB L1 cache : 8 way set associative and 256kB, 512kB or 1M L2 cache : two way set associative 

Figure : PowerPC G4 Block Diagram

The above diagram shows a simplified view of the PowerPC G4 organization, highlighting the placement of the two caches. The core execution unit are two integer arithmetic and logic units, which can execute in parallel, and a floating-point unit with its own multiply, add, and divide components. The data cache feeds both integer and floating-point operations via a load/store unit. The instruction cache, which is read only, feeds into and instruction unit. The L1 caches are eight-way set associative. The L2 cache is a two-way set associative cache with 256K, 512K, or 1MB if memory.

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